1. Field of Invention
The present invention relates to semiconductor integrated circuits in general and in particular to control circuits and method used to reduce power consumption in said semiconductor integrated circuits.
2. Description of Background Art
Most, if not all, equipment or appliances used in the workplace and/or home includes some type of semiconductor integrated circuit component, sometimes called Very Large Scale Integrated (VLSI) circuits, packaged as a chip or module. Even though the circuits are integrated on a substrate, logically they can be partitioned into a number of well known subsystems or components which may include latch array, SRAM, inverters, etc. For optimum performance adequate power must be provided to the subsystems or components. The power is usually provided via a power supply.
One of the concerns is that the power should be utilized to perform useful work and not be dissipated within the subsystem. It has been determined that most of the power dissipated results from leakage current present when the subsystem is in a non-operational mode. Several prior art patents attempt to solve this problem. Examples of such patents include U.S. Pat. Nos. 6,794,914, 6,657,911, 6,380,798, 6,333,571, 6,329,874, 6,222,410, 6,097,113, and 6,034,563.
The prior art also provides other approaches to address this problem. The clock system, composed by flip-flops and clock distribution network, is one of the most power consuming sub-systems in a VLSI circuit. Many techniques have been proposed to reduce clock system dissipation. Among them, Clock-Gating technique used for disabling the clock in inactive portions of the chip is generally considered as a useful approach for power reduction. The Double Gating and NC2MOS techniques apply gating technique separately to the master and slave latch, where a 20% to 40% power reduction is achieved when input switching activity is at about 10%. Since the Clock-Gating is used with lower granularity level, so the area overhead is the major problem for this technique. Other approaches have focused on the dynamic Vt technique, Power-Gating and alternative power supply for the memory core circuits, such as SRAM cells. In order to reduce leakage power dissipation, dynamic Vt technique creates low and high threshold voltages for the transistors with the memory core by applying dynamic body bias through a Local Bias Generator (LBG). In general, this approach requires some additional power supply and circuitry. The Power-Gating technique can significantly reduce the leakage power when memory is in drowsy mode, but the circuit may not retain the data under certain conditions and process variations. The alternative power supply technique uses nMOS pass gates to switch power supply for a memory block in order to reduce leakage power when it is not operational. The major drawback of this approach is that it also requires additional power resources. Further teachings on these techniques are set forth in the following documents:
H. Kawaguchi and T. Sakurai, “A Reduced Clock Swing Flip-Flop (FCSFF) for 63% Power Reduction”, IEEE Journal of Solid-State Circuits, 34(3), March 1999, pp. 405-414.
A. G. M. Strollo, E. Napoli and D. DeCaro, “New Clock-Gating Techniques for Low-Power Flip-Flops”,
C. H. Kim and K. Roy, “Dynamic Vt SRAM: A Leakage tolerant Cache Memory for Low Voltage Microprocessors”, Int. Symp. Low Power Electronics and Design (ISLPED), August 2002, pp. 251-254.
J. W. Tschanz, S. G. Narendra, et al, “Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors”, IEEE Journal of Solid-State Circuits, 38(aa), November 2003, pp. 1838-1845.
M. Power, K. Roy et al., “Gated-Vdd: A Circuit Technique to Reduce Leakage in Cache Memories”, Int. Symp. Low Power Electronics and Design (ISLPED), July 2000, pp. 90-95.
A. Agarwal, H. Li and K. Roy, “A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron”, IEEE Journal of Solid State Circuits, vol. 38, February 2003, pp. 319-328.
P. Elakkumanan, and A. Narasimhan et al., “NC-SRAM—A Low-Leakage Memory Circuit for Ultra Deep Submicron designs”, IEEE SOC conference proceedings, September 2003, p. 3-6.
In view of the above a more efficient apparatus and method to reduce leakage current in VLSI circuits and/or storage systems is required. The reduction of leakage current ultimately results in less power consumption in the VLSI circuit.